Pulse duration discriminator circuit



April 30, 1968 R. VANHOVE PULSE DURATION DISCRIMINATOR CIRCUIT 4 Sheets-Sheet 1 Filed Oct. 8, 1964 FIG. i

DELAY LINE.

C AMPLlFIER WRECTIFIER R. VANHOVE PULSE DURATION DISCRIMINATOR CIRCUIT April 30, 1968 4 Sheets-Sheet Filed Oct. 8, 1964 l I I I l L.

-i. 13...} lvu CIQCUIT P U LSE DURATION REDUCER A ril 30, 1968 R. VANHOVE PULSE DURATION DISCRIMINATOR CIRCUIT 4 Sheets-Sheet 3 Filed Oct. 8, 1964 FIG 5 ADDERN SUBTRACTOR 4 Sheets-Sheet 4 Filed Oct. 8, 1964 l I I dsn) FIG. 6

United States Patent 6 Claims. 61. 328-112) ABSTRACT OF THE DISCLOSURE In order to discriminate pulses of a given duration 1 among longer pulses without causing a blanking between successive pulses, the discriminator comprises n elementary pulse discriminating systems: the blanking is thus reduced to 2/22, and can be rendered as small as necessary.

The present inVentiOn relates to pulse duration discriminator circuits. More particularly the invention relates to pulse duration discriminators, which convert pulses of a duration greater than a given duration, to pulses of duration equal to that duration and corresponding to the leading edge of said pulse, without affecting pulses of a shorter duration and without reducing the resolving power of the discriminator.

The invention is applicable, in particular, to pulse radar receivers with a view to separating echoes from moving targets from those from fixed obstacles, the former echoes having a duration close to that of the transmitted pulse, and the echoes from fixed obstacles generally having a longer duration.

Elementary devices for reducing the duration of long pulses generally include a system including a dilferentiator, followed by a half-wave rectifier; this system makes it possible to retain from a long pulse only its leading edge and has practically no effect on pulses shorter than a given duration. For example, in pulse radar technique, it is usual to employ differentiator circuits with delay lines, which impress a delay approximately equal to the duration or half the duration of the transmitted radar pulse. A known duration discriminator consists of a short-circuited delay line with a delay equal to half the duration of the pulses transmitted, or more generally to half the maximum duration acceptable for the discriminator output pulses, an amplifier and a half-wave rectifier.

This system as well as other more elaborate systems, has the following drawback: behind the received pulse, the system causes at the output a blanking whose duration is equal to the duration of the delay introduced by the short-circuited delay line. It is then impossible to separate two very close pulses: the resolving power of the system is considerably reduced.

The system according to the invention permits, in particular, reducing at will the duration of the blanking which follows the pulse, i.e. bringing out two short pulses or a short and a long pulse, whatever the time interval between these pulses. It comprises essentially n elementary discriminating systems, for example of the delay line type, the minimum admissible interval between two successive input pulses giving rise to two separate output pulses being all the shorter as n is greater. If t is the 3,381,228 Patented Apr. 30, 1968 maximum admissible duration of the output pulses, the system can bring out two successive pulses such that the leading edge of the second is separated from the trailing edge of the first by an interval not less than t/n. It will be seen, therefore that all that is required to make 11 sufiiciently large to permit distinguishing pulses as close to each other as may be necessary is practice.

According to a first embodiment of the invention, the n circuits receive in parallel the pulses to be discriminated, each circuit including a short-circuited delay line, an amplifier and a half-wave rectifier, the rectifier outputs feeding respectively the n inputs of an OR-circuit. The delay lines of the n circuits are different, the delay of on line of a circuit i (i varying from I to n and designatinrz the circuit rank) being equal to ti/Zn.

According to a second embodiment of the invention, the first n-l circuits are identical, each possessing a delay line, a half-wave rectifier and a subtractor which subtracts the output of the rectifier from the input of that circuit; these circuits are connected in cascade, the first receiving the input pulses of the discriminator and each of the following ones resceiving the output pulses from the subtractor of the preceding circuit, the nth circuit not possessing any subtractor. The rectifier outputs of the n circuits feed the n inputs of a linear adder which supplies the desired pulses at its output.

The invention will be better understood from the following description with reference to the drawings, in which:

FIG. 1 is a diagram of a conventional pulse duration discriminator;

FIG. 2 is a diagram which illustrates the mode of operation of the circuit of FIG. 1;

FIG. 3 is a diagram of a first embodiment of the invention;

FIG. 4 is a diagram illustrating the mode of operation of the discriminator of FIG. 3;

FIG. 5 is a diagram of a further embodiment of the invention; and

FIG. 6 is a diagram illustrating the mode of operation of the discriminator of FIG. 5.

The conventional discriminator shown in FIG. 1 comprises a delay line 11, which is short-circuited at one end and connected to the input A of the circuit through a matching resistance 12 at the other end, an amplifier 13, connected to the junction point of a matching resistance 12 and of the delay 11, and a positive half-wave rectifier 14, connected between amplifier 13 and output D- The delay imparted by delay line 11 is equal to [/2, t being the duration of the transmitted pulses in the case of a radar or more generally that of the useful pulses, so that the delay imposed on a signal applied to the delay line and reflected at the short-circuited end thereof is equal to t. The output signals of the delay device have their polarity inverted, so that at point B the signal is equal to the halfsum of the input signals at input A and of the same signals delayed by t and inverted. The coefiicient /2 is introduced by suitably matching the delay line. In this case amplifier 13 of gain 2 gives to the signal at C the amplitude of the incident signal. Rectifier 14 suppresses the negative parts of the output signal from the amplifier.

Curves a, b, c, d of FIG. 2, respectively show the signals, as a function of time T plotted along the abscissa, at points A, B, C, D of the circuit in the case of an input signal consisting of a pulse of duration 1 followed by a pulse of longer duration which is for example the case of an aircraft echo followed by a fixed echo. Curve b shows only the pulses reflected from the shorted end of delay line 11.

Curve b shows the sum at B of the pulses shown in curve b and of pulses whose amplitude is half that of the input pulses.

At output D there appears a pulse of duration 1 and a pulse of the same duration corresponding to the leading edge of the long pulse.

It may be readily seen that with such an arrangement a pulse of a duration shorter or equal to t will appear complete only if its leading edge is spaced by at least t from the trailing edge of the preceding pulse. In partilular, a pulse of duration less than t, appearing at less than t from the trailing edge of the preceding pulse, is completely suppressed if its level is not substantially higher than that of the preceding pulse. Thus, in the case of two aircraft flying close together, the echos of one of them can be completely suppressed.

The arrangement according to the invention shown at FIG. 3 comprises 12 circuits Li (i=1, 2, 3 n). Each circuit is equivalent to that shown in FIG. 1, except that the delay imparted by the delay line is diflFerent. That is to say that between input A3, common to circuits Li and their respective outputs D31 (i: 1, 2, 3 n) are connected elements 11, 12, 13 and 14. However, the delay imparted by delay line is generally not equal to t/2.

Setting =t/n, the respective delays of the delay lines of circuit L1 to Ln are 110/2, (n-l) 0/2 (0/2); that is to say that the line of the circuit of rank i has a delay equal to (n+1-i) 0/2.

The outputs D3i are respectively connected to the n inputs of an OR-circuit 31, which passes to output D3 at each instant the signal which has the highest level appearing at outputs D3i. The OR-circuit is for example a conventional diode circuit.

In FIG. 4, curves d31, d32 d3n represent the signals at the respective output terminals D31, D32 D311 of circuit L1 to L3 of FIG. 3. The input signals are shown at (a) with the time interval therebetween being only 0.

Curve d3 represents the corresponding signals at outputs D3.

The curves of FIG. 4 are readily derived from those shown in FIG. 2. Thus curve d31 is identical with what curve (d) of FIG. 2 would be, if the time interval between the two initial pulses were 0. In this case, while nothing is changed in so far as the first pulse is concerned, the second pulse is cancelled, starting from its leading edge, during the time interval t0 by compensation with the delayed and reversed first pulse.

Curves 132 to d34 are derived from curve (131 merely by modifying the delay imparted by the delay line.

It will be readily seen that a pulse of any duration, whose leading edge appears at time 0 after the end of a preceding pulse will no longer be masked. The time interval 0 is all the shorter as the number n of circuits Li is greater. It is thus possible to discriminate pulses which are much more close to each other than with conventional systems, for the same length 1 of discrimination.

The circuit of FIG. 5 gives the same results with elementary circuits connected in cascade between input A5 and output D5. In this figure, elements G1 to Gn; are identical to each other and to the circuit according to FIG. 1, apart from the fact that the delay imparted by the delay lines of circuits G1 to Gn are equal to 0/2 instead of t, with 0:1/11.

The output voltage from each of the first n-1 circuits (from G1 to Gil-1) is subtracted from the input voltage of the same circuit in a subtractor S1 to Sn1, whose output voltage is then applied to the input of circuit G of the next rank. Outputs D51 to D511 are respectively connected to the 12 inputs of a linear adder 51 which delivers the useful signals.

In the diagram of FIG. 6, curves a, d51 to d511, and d5 4 represent the signals at points A5, D51 to D5n and D5 of the circuit of FIG. 5 respectively, assuming that an input pulse of duration t is followed, a time interval 0 after its trailing edge, by a pulse of duration longer than t.

Curves s1 to slr1 represent the corresponding signals at the outputs of subtractors S1 to Sn-l respectively. The latter may with advantage consist of differential amplifiers.

Here again it will be seen that any pulse appearing after a delay at least equal to 0 will produce an output pulse.

It is to be understood that when the device is used in a pulse radar receiver the input signals are the receiver video-frequency output signals.

The field of application of the invention is of course not restricted to pulse radars. The various elementary circuits, and in particular the delay circuits, will have to be adapted in accordance with the known art to each particular application.

What is claimed is:

1. A pulse duration discriminator for limiting the duration of pulses to a predetermined duration, comprising: 11 elementary circuits, n being an integer greater than one; each of said elementary circuits comprising a pulse input, means for subtracting from said pulse the same pulse delayed by a predetermined duration and a rectifier connected to said means; and pulse combining means coupled to said rectifiers.

2. A pulse duration discriminator for limiting the duration of pulses to a predetermined duration, comprising: a general input; an OR-circuit; n elementary circuits, n being an integer greater than one; each of said elementary circuits comprising a pulse input, means for subtracting from said pulse the same pulse delayed by a predetermined duration and a rectifier connected to said means, said n circuits being connected in parallel between said general input and said OR-circuit.

3. A pulse duration discriminator for limiting the duration of pulses to a predetermined duration, comprising: a general input; a summation device; it elementary circuits, n being an integer greater than one; each of said elementary circuits comprising a pulse input, means for subtracting from said pulse the same pulse delayed by a predetermined duration and a rectifier connected to said means and having an output; each of the n1 first ones of said elementary circuits further comprising a subtracting device coupled to said pulse input of said elementary circuit and to said rectifier output and having an output coupled to the pulse input of the following one of said elementary circuits, the input of the first circuit being coupled to said general input, and said rectifiers being coupled to said summation device.

4. A pulse duration discriminator for limiting the duration of pulses to a predetermined duration, comprising: )1 elementary circuits, n being an integer greater than one; each of said elementary circuits comprising a pulse input, a delay line having two ends, one of said ends being shorted and the other coupled to said pulse input, and a rectifier coupled to said other end; and pulse combining means coupled to said rectifiers.

5. A pulse duration discriminator for limiting the duration of pulses to a predetermined duration 2 comprising; a general input; n elementary circuits, n being an integer greater than one; each ith of said circuits, where i=1,2 n, comprising a pulse input coupled to said general input, a delay line having two ends, one of said ends being coupled to said pulse input and the other being shorted, said line imparting a delay equal to it/2n, and a half-wave rectifier coupled to said one end and having an output; and an OR-circuit having 11 inputs respectively coupled to said outputs of said rectifiers.

6. A pulse duration discriminator for limiting the duration of pulses to a predetermined duration t, comprising a general input; n elementary circuits coupled in cascade and numbered 1 to n, n being an integer greater than one; each of said elementary circuits comprising a pulse input,

a delay line having two ends, one of said ends being coupled to said pulse input and the other being shorted, imparting a delay equal to t/Zn, a rectifier coupled to said second terminal and having an output, each of the n1 first ones of said circuits comprising a subtracting device having two inputs respectively connected to the pulse input of same circuit and to said rectifier output and an output, the pulse input of said first circuit being coupled to said general input, and the input of the ith circuit, where i=2,3 n, being connected to the output of the (il)th circuit; and a summation device hav ing n inputs respectively coupled to said outputs of said rectifiers of said n circuits.

References Cited UNITED STATES PATENTS 2,836,715 5/1958 Spielberg 32858 X 2,984,789 5/1961 OBrien 328120 3,096,484 7/1963 Clark 32867 X 10 JOHN S. HEYMAN, Primary Examiner. 

